1. Field of the Invention
The invention relates to an encoding device, comprising
a first encoder for forming respective first blocks in a first error protection code, PA1 a memory for the storage of data units of the first blocks, PA1 read means for reading a sub-set of the data units, comprising one data unit from each first block, from the memory, and PA1 a second encoder for forming a second block in a second error protection code by encoding the sub-set. PA1 a first decoder for decoding respective first blocks in accordance with a first error correction code, PA1 a memory for the storage of data units of the first blocks, PA1 read means for reading a sub-set of the data units, comprising one data unit from each first block, from the memory, and PA1 a second decoder for decoding the subset in accordance with a second error correction code. PA1 writing data units of a particular first block in the memory distributed among several pages, at least two data units of the particular first block being written on one and the same page on the basis of a first, single page addressing operation, PA1 writing further data units of further first blocks also distributed among the several pages,
The invention also relates to a decoding device, comprising
The invention also relates to a control device for such an encoding or decoding device. An encoding and decoding device of this kind are known from EP 553.515 A (PHN 13.928).
2. Description of the Related Art
The use of an error protection code enables detection and correction of a limited number of incorrect data units in a block. Large numbers of errors, for example so-called burst errors where a number of successive data units are incorrect, cannot be corrected in this manner.
In order to enable correction of burst errors nevertheless, it is known to utilize a so-called product code in which the data is subjected to a first and a second code in such a manner that per block of the second code at the most one data unit of each block of the first code occurs. A burst error in a single block of the first code then corresponds to a single incorrect data unit in a number of blocks of the second code. These errors can be simply corrected by means of the second code.
For the composition of the second blocks it is necessary to collect the data units from a number of first blocks in a memory. This memory must be comparatively large; in the case of digital video recording, for example a memory for more than 100 Kilobytes is required as described in the cited Patent Specification.
Because they have a large capacity, it is advantageous to utilize commercially available DRAMs (dynamic random access memories) for this purpose. The addressing of memory locations in DRAMs requires two address cycles: one to indicate an address of a page, and one to indicate an address within this page. Encoding and decoding of the data units, therefore, is rather time-consuming.